High data reliability, high speed of memory access, and reduced chip size are features that are demanded from semiconductor memory.
In recent years, there has been an effort to increase access speed for semiconductor memory devices. For example, one bank of a multi-bank semiconductor memory device may be refreshed on a semiconductor memory device which supports a so-called per-bank refresh. With per-bank refresh, read or write accesses to the other banks of the memory array can continue while the one bank is being refreshed in the background. In order to initiate one refresh cycle of the memory array for refreshing a row, two commands are issued: at first, a precharge command is issued to close an open row in a bank. Once the row has been precharged, a per-bank refresh command would be issued to perform the refresh in the bank. However, the precharge and per-bank refresh commands occupy two command slots on the command bus, resulting in causing reduction of the average memory bandwidth.
FIG. 1A is a timing diagram of a voltage of a word line associated with a memory row access in a conventional semiconductor memory device. The word line is set to a logic high level responsive to a row activation command (e.g., an activation command “ACTIVATE”, or a per-bank refresh command “REFRESH”), in order to select a page to be opened. The page is open responsive to the activation command, and a read or write access to the page occurs responsive to a read or write command, or a refresh operation of the row in a bank is performed responsive to the per-bank refresh command. If either a different page in the bank is to be opened, or a row in the bank is to be refreshed, and provided the minimum row access cycle time tRAS (e.g., a period between a row access command and row restore) has been met, a precharge command is issued to the bank, and the word line voltage is set to a logic low level. Once the minimum row precharge time tRP has been met, the word line voltage is set to the logic high level again responsive to the per-bank refresh command and the row address may be provided from a refresh counter. Once the tRAS has been met and the page has been refreshed, the word line is set to the logic low level again. In this example, a row cycle time tRC, (e.g., a period of waiting time after a row is activated in a bank before another row can be activated in the same bank, tRAS+tRP) is the same for an activation-precharge cycle as for the per-bank refresh cycle. FIG. 1B is a flow diagram of a command sequence for a per-bank refresh cycle in the conventional semiconductor memory device. The per-bank refresh operation for bank m after accessing column n for read or write (RD/WR m) uses two commands, a precharge command to close the open page, and a per-bank refresh command.